1. Field
Example embodiments relate to non-volatile memory systems and information processing systems including the same, and more particularly, to data-storage memory systems including flash memory devices and information processing systems including the data-storage memory systems.
2. Description of the Related Art
As portable electronic appliances such as a digital camera, a mobile phone such as a smart phone and a personal digital assistant (PDA) have become rapidly wide-spread, non-volatile memory systems have been in great demand. A non-volatile memory device can maintain data even after the power to the memory devices is turned off and has a much simpler horizontal structure of a unit cell than volatile memory devices such as a DRAM and SRAM. For those reasons, the degree of integration of the non-volatile memory device is much higher that the volatile memory device. For example, flash memory devices have become much more wide-spread due to the facilitation of data programming and erasing among the non-volatile memory devices. In addition, the portability of the recent mobile appliances strongly requires lower power consumption for the flash memory devices.
Flash memory devices may be classified into a NAND type and a NOR type according to the structure of the cell array. According to the NAND flash memory device, a plurality of memory cells is connected in series and configured into a single cell string and thus a single contact plug may be needed for the single string. In contrast, according to the NOR flash memory device, each of the memory cells is connected to a bit line and a word line irrespective of other memory cells. Thus, the NAND flash memory device has an advantage of a higher degree of integration while the NOR flash memory device has advantages of high operation speed and excellent random access ability.
A conventional flash memory system including the flash memory devices may detect a memory cell as a programmed cell or an erased cell by comparing the current of the memory cell with that of a reference cell. The currents of the memory cell and the reference cell may be amplified for the conveniences of the comparison by a sensor amplifier. Thus, the conventional flash memory device usually includes a data cell area in which a plurality of memory cells is arranged and electronic data may be stored in each of the memory cells and a reference cell area in which a plurality of reference cells is arranged and the reference current may be detected from each of the reference cells. Recently, the memory cells and the reference cells tend to be formed on the same substrate by the same process to promote manufacturing efficiency of the flash memory device.
To increase the degree of integration of the data cell area of the flash memory device, recent layouts for the flash memory device may reduce the number of the contact structures and thus sufficiently reduce the occupation spaces for the contact structures and the gap spaces between the contact structures and the gate patterns in the cell array region. For example, in a conventional NOR flash memory device, self-aligned source (SAS) rails are formed on the cell array region by a self-aligned etching process and an impurity implantation process in such a way that each of the SAS rails extends in parallel with a word line and a common source line (CSL) is commonly connected to the SAS rails along an active region of a substrate. Thus, the source signals are simultaneously transferred to each of the SAS rails through a single CSL.
According to the conventional NOR flash memory device, the CSL is arranged in parallel with a bit line and a source contact interconnecting the CSL and the SAS rail and a plurality of drain contacts interconnecting drain regions of each cell and the bit line are arranged adjacent with one another along the word line. Therefore, no contact structures are arranged on a first side area of the word line that is covered with the SAS rail and the source contact. The drain contacts are arranged on a second side area of the word line that is symmetrical to the first side area with respect to the word line. Thus, the layout of the conventional NOR flash memory device is usually designed in such way that the neighboring gate structures of the cell spaced apart by the first side area has a gap distance (referred to as first gap distance) smaller than the gap distance of the neighboring gate structures of the cell spaced apart by the second side area (referred to as second gap distance). The first gap distance is smaller than the second gap distance in the cell array region of the conventional NOR flash memory device. As a result, the first side area occupies a smaller space than the second side area in the NOR flash memory device and thus an overall space for the cell array region can be reduced as much as the reduction of the first side area, which increases the degree of integration of the NOR flash memory device.
Pairs of the word lines spaced apart by the second side area are arranged on the cell array region of the substrate at an interval of the SAS rail in the NOR flash memory device. The layout of the conventional NOR flash memory device includes a plurality of the word line pairs spaced apart by a pitch of the first side area that is covered with the SAS rail. The above layout is applied to the reference cell area as well as the data cell area of the NOR flash memory device. Accordingly, the cell transistors arranged along the active region of the substrate are spaced apart alternately by the first gap distance and the second gap distance along a direction perpendicular to the active region on both of the data cell area and the reference cell area.
However, the periodical change of the gap distances between the neighboring gate structures of the cell transistors usually requires periodical variations of process parameters in manufacturing the cell transistors, resulting in the periodical changes of the characteristics of the cell transistors. For example, the threshold voltages and the leakage currents of the cell transistors are periodically changed alternately with respect to the active region of the substrate. The cell transistors along one of the word line pairs at an upper side of the SAS rail (odd word line) has different cell characteristics from the cell transistors along the other of the word line pairs at a lower side of the SAS rail (even word line).
The characteristics change of the cell transistors between the odd and the even word lines becomes much greater due to the differences between etching conditions for the SAS rail and the contact structures and by misalignment of the contact structures. The junction areas of the neighboring cell transistors may be formed at different areas in the first side area due to the various processing errors of the self-aligned etching process and the ion implantation process for forming the SAS rail. Further, the incorrect alignment of the contact structures in the second side area may also deteriorate the cell characteristics of the neighboring cell transistors.
Since the data cell transistors and the reference cell transistors are usually formed on the same substrate by the same process, the above characteristics change of the cell transistors is also found in the reference cell area.
A general data reading operation is performed as follows in the conventional flash memory device. One of the word lines is selected by a row address signal from the data cell area and the reference cell area and one of the bit lines is selected by a column address signal from the data cell area and the reference cell area. Thus, the electrical voltage of a specific memory cell at which the selected word line and bit line crosses in the data cell area is detected as a data current and the electrical voltage of a specific memory cell at which the selected word line and bit line crosses in the reference cell area is detected as a reference current. The data current and the reference current are amplified in a sensor amplifier and the amplified data current and the reference current are compared with each other. The logical value of the data memory cell is determined by the comparison results of the data current and the reference current.
The threshold voltages of the reference cells are set to be an intermediate value between the threshold voltages of the data cells at a programming mode and an erasing mode and thus the reference current is required to be constant irrespective of the odd word lines and the even word lines.
However, the odd word lines and the even word lines have different cell properties due to the differentiation of the manufacturing process and thus the reference current derived from the reference cell connected to the odd word line (first reference current) is usually different from the reference current derived from the reference cell connected to the even word line (second reference current). The charge state of the reference cells may be varied according as which of the odd word line and the even word line is connected to the reference cell. Accordingly, the reference cells cannot generate a single reference current for comparing the data current.
For example, when a high voltage over about 6V is applied to the word line of the reference cell, the difference between the first and the second reference currents is significantly increased over an allowable error range. In addition, the difference between the first and the second reference currents tends to increase in proportion to an operation temperature in a temperature range of about −25° C. to about 100° C. under which most of the flash memory devices are operated.
Accordingly, there is still a need for an improved non-volatile memory device system in which the reference current is stable irrespective of the cell characteristics of the odd and the even word lines.